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CG5982AF 2K x 8 Automotive Dual-port Static RAM
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CG5982AF
2K x 8 Automotive Dual-port Static RAM
Features
* True dual-ported memory cells that allow simultaneous reads of the same memory location * Automotive temperature operation: -40C to +115C * 2K x 8 organization * High-speed access: 55 ns * Low operating power: ICC = 120 mA (max.) * Fully asynchronous operation * Automatic power-down * Master CG5982AF easily expands data bus width to 16 or more bits using slave * BUSY output flag * INT flag for port-to-port communication
Functional Description
The CG5982AF are high-speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CG5982AF can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CG5982AF SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin PLCC version. BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, INT is an interrupt flag indicating that data has been placed in a unique location (7FF for the left port and 7FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CG5982AF is available in a 52-pin PLCC package.
Logic Block Diagram
R/WL CEL OEL * * * * * * R/WR CER OER
I/O7L * * * I/O0L BUSYL A0L
[1]
I/O Control
I/O Control
* I/O7R * * I/O0R [1] BUSYR * A10R * * A0R
* * A10L *
Address Decoder
Memory Array
Address Decoder
CEL OEL
[2] INTL
Arbitration Logic and Interrupt Logic
CER OER R/WR INTR
[2]
R/WL
Notes: 1. CG5982AF (Master): BUSY is open-drain output and requires pull-up resistor. 2. Open drain outputs; pull-up resistor required.
Cypress Semiconductor Corporation Document #: 38-06067 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 6, 2005
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CG5982AF
Pin Configurations
PLCC Top View
BUSY R INTR A10R OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R I/O5R I/O6R BUSYL R/W L CEL VCC NC GND A0L OEL A 10L INT L CER R/W R
A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L
8 9 10 11 12 13 14 15 16 17 18 19 20
7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 CG5982AF 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 I/O0R I/O1R I/O2R I/O3R I/O4R I/O4L I/O5L I/O6L I/O7L
Selection Guide
CG5982AF Maximum Access Time Maximum Operating Current Maximum Standby Current 55 120 45 Unit ns mA mA
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential (Pin 48 to Pin 24) ........................................... -0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State ............................................... -0.5V to +7.0V
DC Input Voltage ............................................-3.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Automotive[3] Ambient Temperature -40C to +115C VCC 5V 10%
Electrical Characteristics Over the Operating Range[4]
CG5982AF Parameter VOH VOL VIH VIL IIX IOZ IOS Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short-Circuit Current[6] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND -5 -5 Test Conditions VCC = Min., IOH = -4.0 mA IOL = 4.0 mA IOL = 16.0 mA[5] 2.2 0.8 +5 +5 -350 Min. 2.4 0.4 0.5 V V A A mA Max. Unit V V
Note: 3. TA is the "instant on" case temperature. 4. See the last page of this specification for Group A subgroup testing information. 5. BUSY and INT pins only. 6. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-06067 Rev. *C
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CG5982AF
Electrical Characteristics Over the Operating Range[4] (continued)
CG5982AF Parameter ICC ISB1 ISB2 ISB3 Description VCC Operating Supply Current Standby Current Both Ports, TTL Inputs Standby Current One Port, TTL Inputs Standby Current Both Ports, CMOS Inputs Standby Current One Port, CMOS Inputs Test Conditions CE = VIL, Outputs Open, f = fMAX[7] CEL and CER > VIH, f = fMAX[7] CEL or CER > VIH, Active Port Outputs Open, f = fMAX[7] Both Ports CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0 One Port CEL or CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX[7] Auto Auto Auto Auto Min. Max. 120 45 90 15 Unit mA mA mA mA
ISB4
Auto
85
mA
Capacitance[8]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 15 10 Unit pF pF
AC Test Loads and Waveforms
5V OUTPUT 30 pF Including Jig and Scope R2 347 R1 893 5V OUTPUT 5 pF Including Jig and Scope R2 347 BUSY OR INT R1 893 5V 281
30 pF
(a)
Equivalent to: THEVENIN EQUIVALENT 250 OUTPUT 1.4V
(b)
3.0V GND 10%
BUSY Output Load (CY7C132/CY7C136 Only)
All input pulses 90% 90% 10% < 5 ns
< 5 ns
Switching Characteristics Over the Operating Range[4, 9]
CG5982AF Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE Read Cycle Time Address to Data Valid[10] Data Hold from Address Change CE LOW to Data Valid[10]
[10]
Description
Min. 55
Max.
Unit ns
55 0 55 25 3
ns ns ns ns ns
OE LOW to Data Valid
OE LOW to Low-Z[8, 11]
Notes: 7. At f = fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/trc and using AC Test Waveforms input levels of GND to 3V. 8. This parameter is guaranteed but not tested. 9. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, output loading of the specified IOL/IOH, and 30-pF load capacitance. 10. AC test conditions use VOH = 1.6V and VOL = 1.4V. 11. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
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CG5982AF
Switching Characteristics Over the Operating Range[4, 9] (continued)
CG5982AF Parameter tHZOE tHZCE tPU tPD Write Cycle[13] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Busy/Interrupt Timing tBLA tBHA tBLC tBHC tPS tWB tWH tBDD tDDD tWDD Interrupt tWINS tEINS tINS tOINR tEINR tINR Timing[15] R/W to INTERRUPT Set Time CE to INTERRUPT Set Time Address to INTERRUPT Set Time OE to INTERRUPT Reset Time[14]
[14]
Description OE HIGH to High-Z[8, 11, 12] CE HIGH to High-Z
[8, 11, 12] [8] [8]
Min.
Max. 25 25
Unit ns ns ns ns ns ns ns ns ns ns ns ns
CE LOW to Power-Up
0 35 55 40 40 2 0 30 20 0 25 0 30 30 30 30 5 0 35 45 Note 15 Note 15 45 45 45 45 45 45
CE HIGH to Power-Down Write Cycle Time CE LOW to Write End
Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start R/W Pulse Width Data Set-up to Write End Data Hold from Write End R/W LOW to High-Z [8] R/W HIGH to Low-Z [8]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
BUSY LOW from Address Match BUSY HIGH from Address BUSY LOW from CE LOW BUSY HIGH from CE HIGH[14] Port Set-up for Priority R/W LOW after BUSY LOW R/W HIGH after BUSY HIGH BUSY HIGH to Valid Data Write Data Valid to Read Data Valid Write Pulse to Data Delay Mismatch[14]
CE to INTERRUPT Reset Time[14] Address to INTERRUPT Reset Time
Notes: 12. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL = 5 pF, as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 13. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 14. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state. 15. A write operation on Port A, where Port A has priority, leaves the data on Port B's outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B's address toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read.
Document #: 38-06067 Rev. *C
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CG5982AF
Switching Waveforms
Read Cycle No. 1 (Either Port-Address Access)[16, 17]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (Either Port-CE/OE)[16, 18]
CE OE tACE tDOE tHZOE tHZCE
tLZOE tLZCE DATA OUT tPU ICC ISB
DATA VALID tPD
Read Cycle No. 3 (Read with BUSY Master)
tRC ADDRESSR R/WR DINR tPS ADDRESSL BUSYL tBLA DOUTL tWDD
Notes: 16. R/W is HIGH for read cycle. 17. Device is continuously selected, CE = VIL and OE = VIL. 18. Address valid prior to or coincident with CE transition LOW.
ADDRESS MATCH tPWE
VALID
ADDRESS MATCH tBHA tBDD VALID tDDD
Document #: 38-06067 Rev. *C
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CG5982AF
Switching Waveforms (continued)
Write Cycle No.1 (OE Three-States Data I/Os--Either Port)[13, 19]
tWC ADDRESS tSCE CE tSA R/W tSD DATAIN DATA VALID tHD tAW tHA tPWE
OE tHZOE HIGH IMPEDANCE DOUT
Write Cycle No. 2 (R/W Three-States Data I/Os--Either Port)[13, 20]
tWC ADDRESS tSCE CE tSA R/W tSD DATAIN tHZWE DOUT
Notes: 19. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required tSD. 20. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.
tHA
tAW
tPWE
tHD
DATA VALID tLZWE HIGH IMPEDANCE
Document #: 38-06067 Rev. *C
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CG5982AF
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration) CEL Valid First:
ADDRESSL,R CEL tPS CER tBLC BUSYR tBHC ADDRESS MATCH
CER Valid First:
ADDRESSL,R CER tPS CEL tBLC BUSYL tBHC ADDRESS MATCH
Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First:
tRC or tWC ADDRESSL ADDRESS MATCH tPS ADDRESSR tBLA BUSYR tBHA ADDRESS MISMATCH
Right Address Valid First:
tRC or tWC ADDRESSR ADDRESS MATCH tPS ADDRESSL tBLA BUSYL tBHA ADDRESS MISMATCH
Document #: 38-06067 Rev. *C
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CG5982AF
Switching Waveforms (continued)
Busy Timing Diagram No. 3 (Write with BUSY, Slave)
CE
tPWE R/W tWB BUSY tWH
Interrupt Timing Diagrams[16]
Left Side Sets INTR:
tWC ADDRESSL CEL R/WL tSA INTR tINS WRITE 7FF tHA
tEINS
tWINS
Right Side Clears INTR:
tRC ADDRESSR tHA CER tEINR R/WR READ 7FF tINR
OER tOINR INTR
Right Side Sets INTL:
tWC ADDRESSR tINS CER tEINS R/WR INTL tSA tWINS WRITE 7FE tHA
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CG5982AF
Interrupt Timing Diagrams[16] (continued)
Left Side Clears INTL:
tRC ADDRESSL CEL tEINR R/WL OEL tOINR INTL tHA READ 7FE tINR
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CG5982AF
Typical DC and AC Characteristics
OUTPUT SOURCE CURRENT (mA) 1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB3 4.5 5.0 5.5 Supply Voltage (V) Normalized Access Time vs. Supply Voltage 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 Supply Voltage (V) Typical Power-on Current vs. Supply Voltage 6.0 TA = 25C 6.0 Normalized Supply Current vs. Supply Voltage NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.6 -55 VCC = 5.0V VIN = 5.0V ISB3 25 Ambient Temperature (C) Normalized Access Time vs. Ambient Temperature 125 Normalized Supply Current vs. Ambient Temperature ICC 120 100 80 60 40 20 0 0 1.0 2.0 3.0 Output Voltage (V) Output Sink Current vs. Output Voltage 4.0 VCC = 5.0V TA = 25C Output Source Current vs. Output Voltage
ICC
OUTPUT SINK CURRENT (mA)
1.6 1.4 1.2 1.0
140 120 100 80 60 40 20 0 0.0
VCC = 5.0V 0.8 0.6 -55
VCC = 5.0V TA = 25C 1.0 2.0 3.0 4.0
25 Ambient Temperature (C) Typical Access Time Change vs. Output Loading
125
Output Voltage (V) Normalized ICC vs. Cycle Time VCC = 5.0V TA = 25C VIN = 5.0V
3.0 NORMALIZED tPC 2.5 2.0 1.5 1.0 0.5 0.0 0
30.0 25.0 DELTA tAA (ns) 20.0 15.0 10.0 5.0
1.25 NORMALIZED ICC
1.0
0.75
VCC =4.5V TA =25C 0 200 400 600 800 1000 Capacitance (pF) 0.50 10 20 30 40
1.0
2.0
3.0
4.0
5.0
0
Supply Voltage (V)
Cycle Frequency (MHz)
Ordering Information
Speed (ns) 55 Ordering Code CG5982AF Package Name J69 Package Type 52-lead Plastic Leaded Chip Carrier Operating Range Automotive
Document #: 38-06067 Rev. *C
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CG5982AF
Package Diagrams
52-lead Plastic Leaded Chip Carrier J69
51-85004-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06067 Rev. *C
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CG5982AF
Document History Page
Document Title: CG5982AF 2K x 8 Automotive Dual-port Static RAM Document Number: 38-06067 REV. ** *A *B ECN 119657 121488 393195 Issue Date 10/10/02 12/09/02 SEE ECN Orig. of Change NIM OOR KGH Description of Change Customized data sheet to meet special requirements for CG5982AF; automotive temperature -40C to +115C; base part in CY7C136 Fixed Typo- changed 5 mA to 5 A (p.2) Included the automotive temperature operation range to the Features section Removed the micron CMOS size and the 52-pin PLCC references from the Features section Added Automotive to the title description Add to external web.
*C
421244
See ECN
ODC
Document #: 38-06067 Rev. *C
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